1. Field of the Invention
The present invention relates to semiconductor integrated circuit configurations and, in particular, to methods and circuitry for reducing interconnect time delays.
2. Discussion of the Related Art
Integrated circuits often include logic signals that must cross the chip or are used as inputs to a number of logic blocks physically located in different areas of the chip. Some of these signals are much slower than others. There are numerous cases in which a "slow" signal crosses a portion of the chip, is logically combined with other signals and then the result, i.e. the output of the combinatorial logic, is returned to the original logic block or sent to logic in a distant part of the chip. With this approach, the interconnect delay can be substantial.